The architecture of most current personal computer (PC) systems, from desktop to server, may be conceptually and schematically illustrated by FIG. 1, to which reference is now made.
PC system 10 typically includes memory 20, which may be embedded within one or more processing units 12, or may be separate therefrom. Processing units 12 are typically coupled with IO devices 14[1]-14[i] via one or more IO buses 16, e.g., peripheral component interconnect (PCI) buses. Some or all of the IO devices may be coupled with an IO bridge 17 which may be coupled with IO bus 16. Optionally, in order to make the connection between processing units 12 and IO devices 14[1]-14[i] quicker, PC system 10 may also include one or more components that communicate with the processing units 12 and control the interaction with memory 20 and the IO buses 16, e.g., a north bridge unit 18.
Processing unit 12 typically includes a Central Processing Unit (CPU) 26 that typically refers to virtual memory addresses or space, which is translated by a memory management unit (MMU) 24 into physical addresses. The physical address is typically used by cache 22 to store data which is frequently accessed for rapid access (although some processor architecture uses virtual addresses for cache access) and for access to memory 20. In addition to ‘virtual to physical’ translation information, the MMU 24 typically contains memory protection information used to grant memory access to its owner, e.g., to the thread or process that requested the memory access. For example, system pages may typically be read only by a privileged process such as an operating system or other privileged process, while memory pages may be accessed by their user space processes.
In the computer architecture described in FIG. 1, there is substantially no memory protection for Direct Memory Access (DMA) done from a DMA-enabled IO device 14[1]-14[i], whether the IO device is directly coupled with IO bus 16 or whether the IO device is coupled with IO bridge 17. In both cases, the IO devices, e.g., IO device 14[1] and 14[i], communicate via DMA engine 28 to directly access memory 20.
As shown in FIG. 1, IO bus 16 is coupled with memory 20 through north bridge unit 18 without the involvement of CPU 26 and MMU 24. Therefore, IO devices 14[1]-14[i] that typically use physical addresses have access to all memory space, both to privileged memory space, such as the memory space of the operating system, and to non-privileged memory space, such as the memory space of applications running on PC system 10. Any mis-configuration of an IO device or hostile re-configuration of IO devices 14 may compromise the stability and integrity of PC system 10 by allowing the DMA engines 28 of IO device 14[1]-14[i] to corrupt any region in memory 20 of system 10.
One method to secure memory is illustrated in FIG. 2, to which reference is now made. System 30 includes one or more IO Memory Management Units (IOMMU) 32. Some or all of 10 devices 14[1]-14[i] may include a local memory IOMMU 32. Alternatively, two or more 10 devices 14[1]-14[i] may share a common IOMMU 32. Each IOMMU 32 typically contains translation and protection tables. Before each transaction between the IO device and the memory, the IOMMU 32 checks the tables to verify that the requested transaction is an allowed transaction.
System 30 has several drawbacks. The translation and protection tables held by IOMMU 32 may be large and contain large amounts of state information. Additionally, if more than one IOMMU 32 is used, the IOMMUs 32 have to be synced to ensure that all IOMMUs 32 have the latest translation and protection tables. Alternatively, if there is one IOMMU 32 shared between multiple units, the resultant tables held by IOMMU 32 may be large and necessitate a fast lookup mechanism in order to achieve reasonable performance time.